The present invention relates to a semiconductor component that has at least one semiconductor chip and a chip carrier with a first surface upon which the semiconductor chip is mounted. The semiconductor chip is connected electrically to soldering connection points. The soldering connection points form a conductive connection through openings in the chip carrier that extend from the first surface of the chip carrier through the chip carrier and as far as a second surface of the chip carrier. At least the semiconductor chip is surrounded by a housing that, for example, has been produced by pressure encapsulation with a pressing compound, in a globe-top technique or by providing a filling underneath in a flip-chip arrangement. Such semiconductor components are known from the prior art, for example from U.S. Pat. No. 4,700,276.
The present invention can be used, for example, in logic or high-frequency semiconductor components. However, it can readily be applied to other types of semiconductor components as well, such as memory components.
Normally, in the case of such semiconductor components, the semiconductor chips are most often mounted on metal leadframes or laminate substrates as chip carriers. Contact is subsequently made with the chip either using the wire bonding technique or the flip-chip technique. The encapsulation of the chip is generally carried out by pressure encapsulation by means of transfer molding. The contact terminals or contact pads of the component are located on the underside of the semiconductor component. Since these components do not have any conventional pin terminals, one speaks of xe2x80x9cleadless componentsxe2x80x9d and of xe2x80x9cleadless chip carriersxe2x80x9d (LCC). Such components from the prior art, having a leadframe or laminate chip carrier are illustrated in FIGS. 1 and 2. Using xe2x80x9cleadless chip componentsxe2x80x9d, as compared with conventional components, a considerably higher number of connections can be implemented using the same area on the printed circuit board. In the case of an identical number of connections, a considerably lower area need be utilized and the overall height of the components can be low at the same time. In particular, in the case of high-frequency applications, advantages result from short signal paths and from the compact design of the components. The good attachment of the component to the printed circuit board, and the small component dimensions have a beneficial effect on the mechanical load bearing capacity of the component and also on its fixing to the printed circuit board.
The designs of such semiconductor components that have previously been disclosed by the prior art have considerable disadvantages, however. For example, although the semiconductor components illustrated in FIG. 1 which have a leadframe chip carrier have a high reliability and stability during production and during the operation of the component, great problems arise when covering the semiconductor component with a pressing compound. Since the leadframe has many openings, great problems result, in the case of one-sided pressure encapsulation, when sealing off the chip carrier in the injection molding tool in such a way that penetration of the pressing compound from the side on which the chip is arranged to the opposite side, on which the connections to the printed circuit board are arranged, is prevented. Therefore, either the complicated application of seals, such as sealing foils, to the underside of the chip carrier is necessary, or the chip carrier is initially structured only from one side and, following the pressure encapsulation of the unstructured part on the underside of the chip carrier, the structuring is removed in an etching step. In both cases, therefore, relatively complicated processing of the semiconductor component is necessary in order to ensure optimal pressure encapsulation. This is necessary in particular if the individual semiconductor chips are to be combined in the form of a matrix array. Although one alternative to this is to pressure-encapsulate each individual chip, the result of this is a greater space requirement for each individual chip, and therefore a lower number of semiconductor chips per unit area. The overall capacity of the production plants which can be achieved with this decreases drastically.
The abovementioned problems when pressure encapsulating the semiconductor components can be avoided if, instead of a leadframe chip carrier, a laminate chip carrier is used. The latter has no openings through which the pressing compound could get onto the underside of the semiconductor component. However, laminate chip carriers have great disadvantages with respect to their reliability and stability, in particular on account of their significantly increased sensitivity to moisture and the risk of the occurrence of soldering shock (popcorn effect).
It is accordingly an object of the invention to provide a semiconductor component having at least one semiconductor chip and a chip carrier which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide such a semiconductor component which has a high reliability and which can be constructed using simple production techniques.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component that includes a chip carrier having a first surface and a second surface. The chip carrier has openings extending from the first surface to the second surface. At least one semiconductor chip is mounted on the first surface. Soldering connection points enable direct contact thereto and are located near the second surface of the chip carrier. The soldering connection points are formed by at least one metal foil that lines the openings and that extends through the openings from the first surface to the second surface. Contact-making points are electrically connected to the semiconductor chip and form electrically conductive connections which extend through the openings in the chip carrier to the soldering connection points. A housing surrounds at least the semiconductor chip. A further metal foil is located between the semiconductor chip and the chip carrier and forms a soldering connection point. The openings include at least one opening that is located underneath the semiconductor chip. The further metal foil extends through the opening that is located underneath the semiconductor chip to the first surface and to the second surface.
In other words, the chip carrier of the semiconductor component has openings which extend from a first surface of the chip carrier through the chip carrier as far as a second surface. The chip carrier is ideally selected from a material which ensures high reliability and stability. In order at the same time to achieve tightness of the semiconductor component when it is being pressure encapsulated with a pressing compound, the openings in the chip carrier are lined with a metal foil which, at the same time, forms the soldering connection points of the semiconductor component. In this case, the metal foil extends from the first surface of the chip carrier through the openings in the direction of the second surface of the chip carrier. The metal foil therefore covers the entire area of the openings in the chip carrier and therefore seals the openings off effectively against possible penetration of the pressing compound. The metal foil can also simultaneously form the contact-making points which are used to produce a conductive connection to the semiconductor chip. However, separate contact-making points can also be provided, which then have a conductive connection to the metal foil. However, contact can be made directly to the soldering connection points from the second surface of the chip carrier. Underneath the semiconductor chip, there is at least one further opening in the chip carrier. In this case, a further metal foil is arranged between the semiconductor chip and the chip carrier. The further metal foil clads this at least one opening and extends from the first surface of the chip carrier through the opening to the second surface of the chip carrier. This metal foil permits the electrical connection of the semiconductor chip at the rear, so that the semiconductor component is well suited, for example, for individual semiconductors. Furthermore, connecting the underside of the chip to the metal foil results in better heat dissipation or shielding or grounding of the semiconductor chip with respect to the printed circuit board. Depending on the size of the opening in the chip carrier underneath the semiconductor chip, a partial or even whole-area connection between the underside of the chip and the printed circuit board can be carried out by soldering the metal foil onto the printed circuit board.
Here, the metal foil can cover part of the first surface which adjoins the rim of the openings. However, provision can also be made for the metal foil to be located only in the openings and not to extend beyond the rim of the openings onto the surface of the chip carrier. If the metal foil is also used as a contact-making point, then in this case, contact can be made with the metal foil in order to produce a conductive connection to the semiconductor chip in the interior of the opening. If, however, the metal foil extends beyond the rim of the opening as far as the first surface of the chip carrier, then contact can also be made with the metal foil in the area of the first surface of the chip carrier. As a rule, a separate piece of metal foil is provided for each of the openings since the latter are most often intended not to have any electrical connection to one another. However, if appropriate a plurality of openings can also be lined by a continuous metal film, where such an electrical connection is indeed desirable.
In the area of the second surface of the chip carrier, provision can be made for the metal film to terminate flush with the second surface or for the metal film to project out of the opening over the second surface. In the last case, the metal foil forms a contact which projects beyond the chip carrier and can be used for the purpose of ensuring a certain spacing between the chip carrier and the printed circuit board. However, provision can also be made for the metal foil in the opening not to extend quite as far as the rim of the opening and therefore not quite as far as the second surface of the chip carrier. The conductive connection to the printed circuit board to be fitted underneath can be produced by appropriate soldered connections with solder material being provided on the printed circuit board and filling the remaining area of the openings with solder material during soldering.
As already mentioned, the chip carrier should consist of the most stable and reliable material. In principle, for example, ceramic or metal can be used. However, the chip carrier preferably consists of a plastic tape, for example of epoxy glass, polyimide or polyester.
For the metal film, correspondingly suitable metals are used, such as copper, copper alloys or iron-nickel alloys.
The metal foil can be introduced into the openings in the chip carrier, for example, by a structured metal layer being laminated onto the chip carrier first, and then being drawn into the openings in the chip carrier by a deep drawing process or an embossing process. Provision can also be made for the metal foil already to be completely structured before being laminated on, so that after being laminated on, the metal foil already lines the openings in the desired manner, and therefore a further embossing or deep-drawing process becomes dispensable. In this way, by means of the shaped metal foil on the underside of the chip carrier, a defined soldering connection point for the solder connection is produced. In the area of the upper side of the chip carrier, the metal foil can be used as a defined contact-making point for the electrical connection of the semiconductor chip to the chip carrier.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component having a chip carrier with openings for making contact, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.